Impact of Bias Temperature Instability on Soft Error Susceptibility

Daniele Rossi; Martin Omana; Cecilia Metra; Alessandro Paccagnella

doi:10.1109/TVLSI.2014.2320307

Impact of Bias Temperature Instability on Soft Error Susceptibility

Daniele Rossi, Martin Omana, Cecilia Metra, Alessandro Paccagnella

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Abstract

In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime.

Original language	English
Pages (from-to)	743 - 751
Number of pages	9
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	23
Issue number	4
DOIs	https://doi.org/10.1109/TVLSI.2014.2320307
Publication status	Published - 30 Apr 2015

Keywords

Aging
bias temperature instability (BTI)
critical charge
soft error (SE)

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10.1109/TVLSI.2014.2320307

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abstract = "In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime.",

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AU - Omana, Martin

AU - Metra, Cecilia

AU - Paccagnella, Alessandro

N1 - © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

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N2 - In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime.

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KW - Aging

KW - bias temperature instability (BTI)

KW - critical charge

KW - soft error (SE)

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JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Impact of Bias Temperature Instability on Soft Error Susceptibility

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Keywords

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