TY - JOUR
T1 - Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation
AU - Zhai, Xiaojun
AU - Bensaali, Faycal
AU - Ramalingam, Soodamani
PY - 2013/3
Y1 - 2013/3
N2 - Number plate localisation is a very important stage in an Automatic Number Plate Recognition (ANPR) system and is computationally intensive. This paper presents a low complexity with high detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplierless architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images respectively, both with a resolution of "640×480" , have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms whilst achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.
AB - Number plate localisation is a very important stage in an Automatic Number Plate Recognition (ANPR) system and is computationally intensive. This paper presents a low complexity with high detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplierless architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images respectively, both with a resolution of "640×480" , have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms whilst achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.
U2 - 10.1049/iet-cds.2012.0064
DO - 10.1049/iet-cds.2012.0064
M3 - Article
SN - 1751-8598
VL - 7
SP - 93
EP - 103
JO - IET Circuits, Devices & Systems
JF - IET Circuits, Devices & Systems
IS - 2
ER -