In-ADC, Rank-Order Filter for Digital Pixel Sensors

Miron Kłosowski, Yichuang Sun, Waldemar Jendernalik, Grzegorz Blakiewicz,, Jacek Jakusz, Stanislaw Szczepanski

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Abstract

This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.
Original languageEnglish
Article numbere13010046
Pages (from-to)1-13
Number of pages13
JournalElectronics
Volume13
Issue number1
Early online date21 Dec 2023
DOIs
Publication statusPublished - 21 Dec 2023

Keywords

  • CMOS image sensor
  • energy efficient rank-order filter
  • focal-plane processing
  • global shutter
  • pixel-level processing
  • single-slope analog-to-digital converter
  • vision chip

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