In-ADC, Rank-Order Filter for Digital Pixel Sensors

Miron Kłosowski; Yichuang Sun; Waldemar Jendernalik; Grzegorz Blakiewicz,; Jacek Jakusz; Stanislaw Szczepanski

doi:10.3390/electronics13010046

In-ADC, Rank-Order Filter for Digital Pixel Sensors

Miron Kłosowski
, Yichuang Sun
, Waldemar Jendernalik
, Grzegorz Blakiewicz,
, Jacek Jakusz
, Stanislaw Szczepanski

Research output: Contribution to journal › Article › peer-review

47 Downloads (Pure)

Abstract

This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.

Original language	English
Article number	e13010046
Pages (from-to)	1-13
Number of pages	13
Journal	Electronics
Volume	13
Issue number	1
Early online date	21 Dec 2023
DOIs	https://doi.org/10.3390/electronics13010046
Publication status	Published - 21 Dec 2023

Keywords

CMOS image sensor
energy efficient rank-order filter
focal-plane processing
global shutter
pixel-level processing
single-slope analog-to-digital converter
vision chip

Access to Document

10.3390/electronics13010046Licence: CC BY

Final_Version
© 2023 The Author(s). Licensee MDPI, Basel, Switzerland. This is an open access article distributed under the terms of the Creative Commons Attribution License (CC BY), https://creativecommons.org/licenses/by/4.0/
Final published version, 3.81 MBLicence: CC BY

Cite this

@article{c834f57280aa43eb8c732c106b8505ca,

title = "In-ADC, Rank-Order Filter for Digital Pixel Sensors",

abstract = "This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.",

keywords = "CMOS image sensor, energy efficient rank-order filter, focal-plane processing, global shutter, pixel-level processing, single-slope analog-to-digital converter, vision chip",

author = "Miron K{\l}osowski and Yichuang Sun and Waldemar Jendernalik and Grzegorz Blakiewicz, and Jacek Jakusz and Stanislaw Szczepanski",

note = "{\textcopyright} 2023 The Author(s). Licensee MDPI, Basel, Switzerland. This is an open access article distributed under the terms of the Creative Commons Attribution License (CC BY), https://creativecommons.org/licenses/by/4.0/",

year = "2023",

month = dec,

day = "21",

doi = "10.3390/electronics13010046",

language = "English",

volume = "13",

pages = "1--13",

journal = "Electronics",

issn = "2079-9292",

publisher = "MDPI Multidisciplinary Digital Publishing Institute",

number = "1",

}

TY - JOUR

T1 - In-ADC, Rank-Order Filter for Digital Pixel Sensors

AU - Kłosowski, Miron

AU - Sun, Yichuang

AU - Jendernalik, Waldemar

AU - Blakiewicz,, Grzegorz

AU - Jakusz, Jacek

AU - Szczepanski, Stanislaw

N1 - © 2023 The Author(s). Licensee MDPI, Basel, Switzerland. This is an open access article distributed under the terms of the Creative Commons Attribution License (CC BY), https://creativecommons.org/licenses/by/4.0/

PY - 2023/12/21

Y1 - 2023/12/21

N2 - This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.

AB - This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.

KW - CMOS image sensor

KW - energy efficient rank-order filter

KW - focal-plane processing

KW - global shutter

KW - pixel-level processing

KW - single-slope analog-to-digital converter

KW - vision chip

U2 - 10.3390/electronics13010046

DO - 10.3390/electronics13010046

M3 - Article

SN - 2079-9292

VL - 13

SP - 1

EP - 13

JO - Electronics

JF - Electronics

IS - 1

M1 - e13010046

ER -

In-ADC, Rank-Order Filter for Digital Pixel Sensors

Abstract

Keywords

Access to Document

Fingerprint

Cite this