Intelligent co-operative PIM architecture for image analysis and pattern recognition

Z. Ahmed, R. Sotudeh, D.M.A. Hussain

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

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    Computer memory systems are increasingly a bottleneck limiting application performance. Processor-In-Memory (PIM) architectures, which capitalize on merging the processing unit with its memory unit on the same chip [1], promise to remove this limitation by providing a tremendous increase in available memory bandwidth and significant reduction in memory latency for a specific class of computing that deals with significant amount of data with relatively simple operations. Many image processing and pattern recognition applications fall into this category. In this paper, some key characteristics with design philosophy of an intelligent co-operative PIM architecture (CIM) are discussed, and examples of image analysis algorithm that can run on it are given.
    Original languageEnglish
    Title of host publicationProcs of the International MultiConference of Engineers and Computer Scientists 2010, IMECS 2010
    PublisherIAENG, International Association of Engineers
    ISBN (Print)978-988170128-2
    Publication statusPublished - 2010


    • co-operative intelligent memory (CIM)
    • CPU major
    • CPU minor
    • observer
    • processor-in-memory (PIM)
    • shared memory
    • task optimizer


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