Intelligent co-operative PIM architecture for image analysis and pattern recognition

Z. Ahmed; R. Sotudeh; D.M.A. Hussain

Intelligent co-operative PIM architecture for image analysis and pattern recognition

Z. Ahmed, R. Sotudeh, D.M.A. Hussain

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Abstract

Computer memory systems are increasingly a bottleneck limiting application performance. Processor-In-Memory (PIM) architectures, which capitalize on merging the processing unit with its memory unit on the same chip [1], promise to remove this limitation by providing a tremendous increase in available memory bandwidth and significant reduction in memory latency for a specific class of computing that deals with significant amount of data with relatively simple operations. Many image processing and pattern recognition applications fall into this category. In this paper, some key characteristics with design philosophy of an intelligent co-operative PIM architecture (CIM) are discussed, and examples of image analysis algorithm that can run on it are given.

Original language	English
Title of host publication	Procs of the International MultiConference of Engineers and Computer Scientists 2010, IMECS 2010
Publisher	IAENG, International Association of Engineers
Pages	2236-2240
ISBN (Print)	978-988170128-2
Publication status	Published - 2010

Keywords

co-operative intelligent memory (CIM)
CPU major
CPU minor
observer
processor-in-memory (PIM)
shared memory
task optimizer

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Cite this

@inproceedings{188cd39482df4b6f90615a69f6acdd18,

title = "Intelligent co-operative PIM architecture for image analysis and pattern recognition",

abstract = "Computer memory systems are increasingly a bottleneck limiting application performance. Processor-In-Memory (PIM) architectures, which capitalize on merging the processing unit with its memory unit on the same chip [1], promise to remove this limitation by providing a tremendous increase in available memory bandwidth and significant reduction in memory latency for a specific class of computing that deals with significant amount of data with relatively simple operations. Many image processing and pattern recognition applications fall into this category. In this paper, some key characteristics with design philosophy of an intelligent co-operative PIM architecture (CIM) are discussed, and examples of image analysis algorithm that can run on it are given.",

keywords = "co-operative intelligent memory (CIM), CPU major, CPU minor, observer, processor-in-memory (PIM), shared memory, task optimizer",

author = "Z. Ahmed and R. Sotudeh and D.M.A. Hussain",

note = "Original article can be found at : http://www.iaeng.org/ Copyright International Association of Engineers",

year = "2010",

language = "English",

isbn = "978-988170128-2",

pages = "2236--2240",

booktitle = "Procs of the International MultiConference of Engineers and Computer Scientists 2010, IMECS 2010",

publisher = "IAENG, International Association of Engineers",

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Intelligent co-operative PIM architecture for image analysis and pattern recognition. / Ahmed, Z.; Sotudeh, R.; Hussain, D.M.A.
Procs of the International MultiConference of Engineers and Computer Scientists 2010, IMECS 2010. IAENG, International Association of Engineers, 2010. p. 2236-2240.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Intelligent co-operative PIM architecture for image analysis and pattern recognition

AU - Ahmed, Z.

AU - Sotudeh, R.

AU - Hussain, D.M.A.

N1 - Original article can be found at : http://www.iaeng.org/ Copyright International Association of Engineers

PY - 2010

Y1 - 2010

N2 - Computer memory systems are increasingly a bottleneck limiting application performance. Processor-In-Memory (PIM) architectures, which capitalize on merging the processing unit with its memory unit on the same chip [1], promise to remove this limitation by providing a tremendous increase in available memory bandwidth and significant reduction in memory latency for a specific class of computing that deals with significant amount of data with relatively simple operations. Many image processing and pattern recognition applications fall into this category. In this paper, some key characteristics with design philosophy of an intelligent co-operative PIM architecture (CIM) are discussed, and examples of image analysis algorithm that can run on it are given.

AB - Computer memory systems are increasingly a bottleneck limiting application performance. Processor-In-Memory (PIM) architectures, which capitalize on merging the processing unit with its memory unit on the same chip [1], promise to remove this limitation by providing a tremendous increase in available memory bandwidth and significant reduction in memory latency for a specific class of computing that deals with significant amount of data with relatively simple operations. Many image processing and pattern recognition applications fall into this category. In this paper, some key characteristics with design philosophy of an intelligent co-operative PIM architecture (CIM) are discussed, and examples of image analysis algorithm that can run on it are given.

KW - co-operative intelligent memory (CIM)

KW - CPU major

KW - CPU minor

KW - observer

KW - processor-in-memory (PIM)

KW - shared memory

KW - task optimizer

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M3 - Conference contribution

SN - 978-988170128-2

SP - 2236

EP - 2240

BT - Procs of the International MultiConference of Engineers and Computer Scientists 2010, IMECS 2010

PB - IAENG, International Association of Engineers

ER -

Intelligent co-operative PIM architecture for image analysis and pattern recognition

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Keywords

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