TY - JOUR
T1 - Low-Cost On-Chip Clock Jitter Measurement Scheme
AU - Omana, Martin
AU - Rossi, Daniele
AU - Giaffreda, Daniele
AU - Metra, Cecilia
AU - Mak, TM
AU - Raman, Asifur
AU - Tam, Simon
N1 - This document is the Accepted Manuscript version of the following article: Martin Omaῆa, Daniele Rossi, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Asifur Rahman, and Simon Tam, ‘Low-Cost On-Chip Clock Jitter Measurement Scheme’, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23 (3): 435-443, April 2014, DOI:
https://doi.org/10.1109/TVLSI.2014.2312431.
© 2014 IEEE.
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PY - 2015/3/1
Y1 - 2015/3/1
N2 - In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution.
AB - In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution.
KW - Clock jitter
KW - high performance microprocessors
KW - jitter measurement
KW - phase measurement
U2 - 10.1109/TVLSI.2014.2312431
DO - 10.1109/TVLSI.2014.2312431
M3 - Article
VL - 23
SP - 435
EP - 443
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 3
ER -