Low-Cost On-Chip Clock Jitter Measurement Scheme

Martin Omana, Daniele Rossi, Daniele Giaffreda, Cecilia Metra, TM Mak, Asifur Raman, Simon Tam

    Research output: Contribution to journalArticlepeer-review

    3 Citations (Scopus)
    26 Downloads (Pure)


    In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution.
    Original languageEnglish
    Pages (from-to)435 - 443
    Number of pages9
    JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
    Issue number3
    Early online date11 Apr 2014
    Publication statusPublished - 1 Mar 2015


    • Clock jitter
    • high performance microprocessors
    • jitter measurement
    • phase measurement


    Dive into the research topics of 'Low-Cost On-Chip Clock Jitter Measurement Scheme'. Together they form a unique fingerprint.

    Cite this