Memory management in output-buffering packet-switch design

J. Xu, R. Sotudeh

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

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    The most pressing problem in design of a synchronous buffer-memory system in high-speed packet switches is memory bandwidth. If there are multiple packets heading for the same buffer while the buffer cannot consume them simultaneously, some of the packets will have to be dropped. Two approaches are explored to resolve this problem in this paper. One is via improving the buffer-memory architecture, and the other is via replacing clock-based synchronous technology with handshaking-based asynchronous technology. Both approaches are implemented and the results of experiments run to evaluate several aspects of the implementations are compared.
    Original languageEnglish
    Title of host publicationInt Symp on Signals Circuits and Systems 2005 (ISSCS 2005) 1
    PublisherInstitute of Electrical and Electronics Engineers (IEEE)
    Publication statusPublished - 2005


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