In this paper we show that power gating techniques become more effective during their lifetime, since the aging of sleep transistors (STs) due to negative bias temperature instability (NBTI) drastically reduces leakage power. Based on this property, we propose an NBTI and leakage aware ST design method for reliable and energy efficient power gating. Through SPICE simulations, we show lifetime extension up to 19.9x and average leakage power reduction up to 14.4% compared to standard STs design approach without additional area overhead. Finally, when a maximum 10-year lifetime target is considered, we show that the proposed method allows multiple beneficial options compared to a standard STs design method: either to improve circuit operating frequency up to 9.53% or to reduce ST area overhead up to 18.4%.
|Title of host publication||Proceedings - 2015 20th IEEE European Test Symposium, ETS 2014|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Publication status||Published - 29 Jun 2015|
|Event||2015 20th IEEE European Test Symposium, ETS 2014 - Cluj-Napoca|
Duration: 25 May 2015 → 29 May 2015
|Conference||2015 20th IEEE European Test Symposium, ETS 2014|
|Period||25/05/15 → 29/05/15|