Power consumption of fault tolerant busses

Daniele Rossi, André K. Nieuwland, Steven V.E.S. Van Dijk, Richard P. Kleihorst, Cecilia Metra

    Research output: Contribution to journalArticlepeer-review

    20 Citations (Scopus)


    On-chip interconnects in very deep submicrometer technology are becoming more sensitive and prone to errors caused by power supply noise, crosstalk, delay variations and transient faults. Error-correcting codes (ECCs) can be employed in order to provide signal transmission with the necessary data integrity. In this paper, the impact of ECCs to encode the information on a very deep submicrometer bus on bus power consumption is analyzed. To fulfill this purpose, both the bus wires (with mutual capacitances, drivers, repeaters and receivers) and the encodingdecoding circuitry are accounted for. After a detailed analysis of power dissipation in deep submicrometer fault-tolerant busses using Hamming single ECCs, it is shown that no power saving is possible by choosing among different Hamming codes. A novel scheme, called Dual Rail, is then proposed. It is shown that Dual Rail, combined with a proper bus layout, can provide a reduction of energy consumption. In particular, it is shown how the passive elements of the bus (bottom and mutual wire capacitances), active elements of the bus (buffers) and error-correcting circuits contribute to power consumption, and how different tradeoffs can be achieved. The analysis presented in this paper has been performed considering a realistic bus structure, implemented in a standard 0.13-$\mu{\hbox{m}}$ CMOS technology.

    Original languageEnglish
    Article number4469920
    Pages (from-to)542-552
    Number of pages11
    JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
    Issue number5
    Publication statusPublished - May 2008


    • Bus
    • Error-correcting codes (ECCs)
    • Fault tolerance
    • Power consumption
    • Signal integrity


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