Principles of timing anomalies in superscalar processors

I. Wenzel, Raimund Kirner, P. Puschner, B. Rieder

Research output: Chapter in Book/Report/Conference proceedingConference contribution

31 Citations (Scopus)
50 Downloads (Pure)

Abstract

The counter-intuitive timing behavior of certain features in superscalar processors that cause severe problems for existing worst-case execution time analysis (WCET) methods is called timing anomalies. In this paper, we identify structural sources potentially causing timing anomalies in superscalar pipelines. We provide examples for cases where timing anomalies can arise in much simpler hardware architectures than commonly supposed (i.e., even in hardware containing only in-orderfunctional units). We elaborate the general principle behind timing anomalies and propose a general criterion (resource allocation criterion) that provides a necessary (but not sufficient) condition for the occurrence of timing anomalies in a processor. This principle allows to state the absence of timing anomalies for a specific combination of hardware and software and thus forms a solid theoretic foundation for the time-predictable execution of real-time software on complex processor hardware.
Original languageEnglish
Title of host publicationIn: Procs of Fifth International Conference on Quality Software
Subtitle of host publicationQSIC 2005
EditorsKY Cai, A Ohnishi, MF Lau
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages295-303
Number of pages9
ISBN (Print)0-7695-2472-9
DOIs
Publication statusPublished - 2005
Event5th International Conference on Quality Software (QSIC 2005) - Melbourne
Duration: 19 Sept 200520 Sept 2005

Conference

Conference5th International Conference on Quality Software (QSIC 2005)
CityMelbourne
Period19/09/0520/09/05

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