TY - GEN
T1 - Principles of timing anomalies in superscalar processors
AU - Wenzel, I.
AU - Kirner, Raimund
AU - Puschner, P.
AU - Rieder, B.
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PY - 2005
Y1 - 2005
N2 - The counter-intuitive timing behavior of certain features in superscalar processors that cause severe problems for existing worst-case execution time analysis (WCET) methods is called timing anomalies. In this paper, we identify structural sources potentially causing timing anomalies in superscalar pipelines. We provide examples for cases where timing anomalies can arise in much simpler hardware architectures than commonly supposed (i.e., even in hardware containing only in-orderfunctional units). We elaborate the general principle behind timing anomalies and propose a general criterion (resource allocation criterion) that provides a necessary (but not sufficient) condition for the occurrence of timing anomalies in a processor. This principle allows to state the absence of timing anomalies for a specific combination of hardware and software and thus forms a solid theoretic foundation for the time-predictable execution of real-time software on complex processor hardware.
AB - The counter-intuitive timing behavior of certain features in superscalar processors that cause severe problems for existing worst-case execution time analysis (WCET) methods is called timing anomalies. In this paper, we identify structural sources potentially causing timing anomalies in superscalar pipelines. We provide examples for cases where timing anomalies can arise in much simpler hardware architectures than commonly supposed (i.e., even in hardware containing only in-orderfunctional units). We elaborate the general principle behind timing anomalies and propose a general criterion (resource allocation criterion) that provides a necessary (but not sufficient) condition for the occurrence of timing anomalies in a processor. This principle allows to state the absence of timing anomalies for a specific combination of hardware and software and thus forms a solid theoretic foundation for the time-predictable execution of real-time software on complex processor hardware.
U2 - 10.1109/QSIC.2005.49
DO - 10.1109/QSIC.2005.49
M3 - Conference contribution
SN - 0-7695-2472-9
SP - 295
EP - 303
BT - In: Procs of Fifth International Conference on Quality Software
A2 - Cai, KY
A2 - Ohnishi, A
A2 - Lau, MF
PB - IEEE
T2 - 5th International Conference on Quality Software (QSIC 2005)
Y2 - 19 September 2005 through 20 September 2005
ER -