TY - JOUR
T1 - Single-Slope ADC with Embedded Convolution Filter for Global-Shutter CMOS Image Sensors
AU - Kłosowski, Miron
AU - Sun, Yichuang
AU - Jendernalik, Waldemar
AU - Blakiewicz,, Grzegorz
AU - Jakusz, Jacek
AU - Szczepanski, Stanislaw
N1 - © 2023 IEEE. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/TCSII.2023.3266714
PY - 2023/9/1
Y1 - 2023/9/1
N2 - This brief presents an analog-to-digital converter (ADC) suitable for acquisition and processing of images in the global-shutter mode at the pixel level. The ADC consists of an analog comparator, a multi-directional shift register for the comparator states, and a 16-bit reversible binary counter with programmable step size. It works in the traditional single-slope mode. The novelty is that during each step of the reference ramp, neighboring pixels can exchange status information. During the conversion, the direction and step size of the counter are set globally to realize the corresponding coefficient of a convolution kernel. This technique does not slow down the conversion when used for small kernels (3× 3) and does not significantly increase sensor noise. Convolution windows of arbitrary size can be implemented. The concept was verified in an experimental 64×64 imaging array implemented in 180 nm CMOS technology.
AB - This brief presents an analog-to-digital converter (ADC) suitable for acquisition and processing of images in the global-shutter mode at the pixel level. The ADC consists of an analog comparator, a multi-directional shift register for the comparator states, and a 16-bit reversible binary counter with programmable step size. It works in the traditional single-slope mode. The novelty is that during each step of the reference ramp, neighboring pixels can exchange status information. During the conversion, the direction and step size of the counter are set globally to realize the corresponding coefficient of a convolution kernel. This technique does not slow down the conversion when used for small kernels (3× 3) and does not significantly increase sensor noise. Convolution windows of arbitrary size can be implemented. The concept was verified in an experimental 64×64 imaging array implemented in 180 nm CMOS technology.
KW - CMOS image sensor
KW - Clocks
KW - Convolution
KW - Image edge detection
KW - Kernel
KW - Latches
KW - Optimization
KW - Shift registers
KW - energy efficient convolution filter
KW - focal-plane processing
KW - global shutter
KW - pixel-level processing
KW - single-slope analog-to-digital converter
KW - vision chip
UR - http://www.scopus.com/inward/record.url?scp=85153348444&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2023.3266714
DO - 10.1109/TCSII.2023.3266714
M3 - Article
SN - 1549-7747
VL - 70
SP - 3258
EP - 3262
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 9
ER -