Static Instruction Scheduling for the HARP Multiple-Instruction-Issue Architecture

S.M. Gray, R.G. Adams, G.J. Green, G.B. Steven

Research output: Contribution to journalArticlepeer-review


HARP is a new multiple-instruction-issue architecture developed at the University of Hertfordshire. This paper describes the essential features of the HARP machine model and presents two compile-time scheduling techniques, called local and conditional compaction, which have been developed for the architecture. Local compaction schedules the instructions within a basic block. Conditional compaction uses HARP's conditional execution mechanism to schedule instructions across basic block boundaries. This paper reports performance measurements obtained using simulations of the model. These results indicate that a HARP processor will achieve sustained instruction execution rates in excess of two sequential instructions per cycle for compiled, integer, general-purpose computations.
Original languageEnglish
Pages (from-to)415-424
JournalMicroprocessors and Microsystems
Issue number7
Publication statusPublished - 1993


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