Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

Mauricio D. Gutierrez, Vasileios Tenentes, Daniele Rossi, Tom J. Kazmierski

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    2 Citations (Scopus)
    29 Downloads (Pure)


    Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in the presence of faults not all workloads are equally susceptible to errors. In this paper, we present a low power fault tolerance design technique that selects and protects the most susceptible workload. We propose to rank the workload susceptibility as the likelihood of any error to bypass the logic masking of the circuit and propagate to its outputs. The susceptible workload is protected by a partial Triple Modular Redundancy (TMR) scheme. We evaluate the proposed technique on timing-independent and timing-dependent errors induced by permanent and transient faults. In comparison with unranked selective fault tolerance approach, we demonstrate a) a similar error coverage with a 39.7% average reduction of the area overhead or b) a 86.9% average error coverage improvement for a similar area overhead. For the same area overhead case, we observe an error coverage improvement of 53.1% and 53.5% against permanent stuck-at and transition faults, respectively, and an average error coverage improvement of 151.8% and 89.0% against timing-dependent and timing-independent transient faults, respectively. Compared to TMR, the proposed technique achieves an area and power overhead reduction of 145.8% to 182.0%.

    Original languageEnglish
    Pages (from-to)463-477
    Number of pages15
    JournalJournal of Electronic Testing: Theory and Applications (JETTA)
    Issue number4
    Publication statusPublished - 20 Jun 2017


    • Selective fault tolerance
    • Workload susceptibility analysis
    • Susceptible workload
    • Output deviations
    • Permanent faults
    • Transient Faults


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