The challenges of efficient code-generation for massively parallel architectures

Jason M. McGuiness, Colin Egan, B. Christianson, Guang Gao

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    1 Citation (Scopus)
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    Abstract

    Overcoming the memory wall [15] may be achieved by increasing the bandwidth and reducing the latency of the processor to memory connection, for example by implementing Cellular architectures, such as the IBM Cyclops. Such massively parallel architectures have sophisticated memory models. In this paper we used DIMES (the Delaware Iterative Multiprocessor Emulation System), developed by CAPSL at the University of Delaware, as a hardware evaluation tool for cellular architectures. The authors contend that there is an open question regarding the potential, ideal approach to parallelism from the programmer's perspective. For example, at language-level such as UPC or HPF, or using trace-scheduling, or at a library-level, for example OpenMP or POSIX-threads. To investigate this, we have chosen to use a threaded Mandelbrot-set generator with a work-stealing algorithm to evaluate the DIMES cthread programming model for writing a simple multi-threaded program.

    Original languageEnglish
    Pages (from-to)416-422
    Number of pages7
    JournalLecture Notes in Computer Science (LNCS)
    Volume4186
    DOIs
    Publication statusPublished - 2006

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