The development of iHARP: a multiple instruction issue processor chip

G.B. Steven, R.G. Adams, P. Findlay, S.A. Trainis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Abstract

During the last decade RISC ideas on processor architecture have become widely accepted. RISC architectures achieve significant performance advantages over CISC architectures by striving to execute one instruction per cycle. However, a traditional RISC architemre can never execute more than one instruction per cycle. Achieving further performance improvements beyond RISC depends on developing processors which fetch and execute more than one operation in each processor cycle.
Original languageEnglish
Title of host publicationProcs of the IEE Colloquium on RISC Architectures and Applications
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1
Number of pages5
Volume2
Publication statusPublished - 1991

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