The development of iHARP: a multiple instruction issue processor chip

G.B. Steven; R.G. Adams; P. Findlay; S.A. Trainis

The development of iHARP: a multiple instruction issue processor chip

G.B. Steven
, R.G. Adams
, P. Findlay
, S.A. Trainis

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Abstract

During the last decade RISC ideas on processor architecture have become widely accepted. RISC architectures achieve significant performance advantages over CISC architectures by striving to execute one instruction per cycle. However, a traditional RISC architemre can never execute more than one instruction per cycle. Achieving further performance improvements beyond RISC depends on developing processors which fetch and execute more than one operation in each processor cycle.

Original language	English
Title of host publication	Procs of the IEE Colloquium on RISC Architectures and Applications
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1
Number of pages	5
Volume	2
Publication status	Published - 1991

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title = "The development of iHARP: a multiple instruction issue processor chip",

abstract = "During the last decade RISC ideas on processor architecture have become widely accepted. RISC architectures achieve significant performance advantages over CISC architectures by striving to execute one instruction per cycle. However, a traditional RISC architemre can never execute more than one instruction per cycle. Achieving further performance improvements beyond RISC depends on developing processors which fetch and execute more than one operation in each processor cycle.",

author = "G.B. Steven and R.G. Adams and P. Findlay and S.A. Trainis",

note = "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.---- Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.",

year = "1991",

language = "English",

volume = "2",

pages = "1",

booktitle = "Procs of the IEE Colloquium on RISC Architectures and Applications",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

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T1 - The development of iHARP: a multiple instruction issue processor chip

AU - Steven, G.B.

AU - Adams, R.G.

AU - Findlay, P.

AU - Trainis, S.A.

N1 - This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.---- Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

PY - 1991

Y1 - 1991

N2 - During the last decade RISC ideas on processor architecture have become widely accepted. RISC architectures achieve significant performance advantages over CISC architectures by striving to execute one instruction per cycle. However, a traditional RISC architemre can never execute more than one instruction per cycle. Achieving further performance improvements beyond RISC depends on developing processors which fetch and execute more than one operation in each processor cycle.

AB - During the last decade RISC ideas on processor architecture have become widely accepted. RISC architectures achieve significant performance advantages over CISC architectures by striving to execute one instruction per cycle. However, a traditional RISC architemre can never execute more than one instruction per cycle. Achieving further performance improvements beyond RISC depends on developing processors which fetch and execute more than one operation in each processor cycle.

M3 - Conference contribution

VL - 2

SP - 1

BT - Procs of the IEE Colloquium on RISC Architectures and Applications

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

The development of iHARP: a multiple instruction issue processor chip

Abstract

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