Despite the widely held belief that the most limiting factor in processor performance is the memory hierarchy, much of the recent research into multiple instruction issue techniques assumes a perfect cache structure with a 100% hit rate. This paper attempts to rectify this imbalance by quantifying the performance impact of if incorporating a realistic cache structure into a high-performance superscalar architecture. A highly parameterised cache simulator is integrated into a minimal superscalar architecture, the Hatfield Superscalar Architecture (HSA), that uses static instruction scheduling and in-order instruction issue. Two main studies are presented. First, the impact of a cache on unscheduled code is compared to the impact of a cache on scheduled code. Second, the speedup achieved through static instruction scheduling with a perfect cache is compared to the speedup achieved with a series of cache sizes.
|Name||UH Computer Science Technical Report|
|Publisher||University of Hertfordshire|