The impact of a realistic cache structure on a high performance Superscalar architecture

D. Tate

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    Abstract

    Despite the widely held belief that the most limiting factor in processor performance is the memory hierarchy, much of the recent research into multiple instruction issue techniques assumes a perfect cache structure with a 100% hit rate. This paper attempts to rectify this imbalance by quantifying the performance impact of if incorporating a realistic cache structure into a high-performance superscalar architecture. A highly parameterised cache simulator is integrated into a minimal superscalar architecture, the Hatfield Superscalar Architecture (HSA), that uses static instruction scheduling and in-order instruction issue. Two main studies are presented. First, the impact of a cache on unscheduled code is compared to the impact of a cache on scheduled code. Second, the speedup achieved through static instruction scheduling with a perfect cache is compared to the speedup achieved with a series of cache sizes.
    Original languageEnglish
    PublisherUniversity of Hertfordshire
    Publication statusPublished - 1998

    Publication series

    NameUH Computer Science Technical Report
    PublisherUniversity of Hertfordshire
    Volume319

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