Time-predictable task preemption for real-time systems with direct-mapped instruction cache

Raimund Kirner, Peter Puschner

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
34 Downloads (Pure)

Abstract

Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded software is generally increasing, it becomes more and more complex to verify the correct temporal behavior of software, running on this high-end embedded computer systems. To achieve time-predictability the authors introduced a very rigid software execution model with distribution being realized based on the time-triggered communication model. In this paper we analyze the time-predictability of a preempting task-activation, running on a hardware with direct-mapped instruction caches. As one result we analyze why a task-preemption driven by a clock interrupt is not suitable to guarantee time-predictability. As a second result, we present a time-predictable task-preemption driven by an instruction counter.
Original languageEnglish
Title of host publicationIn: Procs of 10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing
EditorsM DeMiguel, V Kalogeraki, DH Kim
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages87-92
Number of pages6
ISBN (Print)0-7695-2765-5
DOIs
Publication statusPublished - 2007
Event10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing - Santorini Isl
Duration: 7 May 20079 May 2007

Conference

Conference10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing
CitySantorini Isl
Period7/05/079/05/07

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