Time-predictable task preemption for real-time systems with direct-mapped instruction cache

Raimund Kirner; Peter Puschner

doi:10.1109/ISORC.2007.56

Time-predictable task preemption for real-time systems with direct-mapped instruction cache

Raimund Kirner, Peter Puschner

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

37 Downloads (Pure)

Abstract

Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded software is generally increasing, it becomes more and more complex to verify the correct temporal behavior of software, running on this high-end embedded computer systems. To achieve time-predictability the authors introduced a very rigid software execution model with distribution being realized based on the time-triggered communication model. In this paper we analyze the time-predictability of a preempting task-activation, running on a hardware with direct-mapped instruction caches. As one result we analyze why a task-preemption driven by a clock interrupt is not suitable to guarantee time-predictability. As a second result, we present a time-predictable task-preemption driven by an instruction counter.

Original language	English
Title of host publication	In: Procs of 10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing
Editors	M DeMiguel, V Kalogeraki, DH Kim
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	87-92
Number of pages	6
ISBN (Print)	0-7695-2765-5
DOIs	https://doi.org/10.1109/ISORC.2007.56
Publication status	Published - 2007
Event	10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing - Santorini Isl Duration: 7 May 2007 → 9 May 2007

Conference

Conference	10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing
City	Santorini Isl
Period	7/05/07 → 9/05/07

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10.1109/ISORC.2007.56

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“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”
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Kirner, R., & Puschner, P. (2007). Time-predictable task preemption for real-time systems with direct-mapped instruction cache. In M. DeMiguel, V. Kalogeraki, & DH. Kim (Eds.), In: Procs of 10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (pp. 87-92). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ISORC.2007.56

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title = "Time-predictable task preemption for real-time systems with direct-mapped instruction cache",

abstract = "Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded software is generally increasing, it becomes more and more complex to verify the correct temporal behavior of software, running on this high-end embedded computer systems. To achieve time-predictability the authors introduced a very rigid software execution model with distribution being realized based on the time-triggered communication model. In this paper we analyze the time-predictability of a preempting task-activation, running on a hardware with direct-mapped instruction caches. As one result we analyze why a task-preemption driven by a clock interrupt is not suitable to guarantee time-predictability. As a second result, we present a time-predictable task-preemption driven by an instruction counter.",

author = "Raimund Kirner and Peter Puschner",

note = "“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"} “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”; 10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing ; Conference date: 07-05-2007 Through 09-05-2007",

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Kirner, R & Puschner, P 2007, Time-predictable task preemption for real-time systems with direct-mapped instruction cache. in M DeMiguel, V Kalogeraki & DH Kim (eds), In: Procs of 10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing. Institute of Electrical and Electronics Engineers (IEEE), pp. 87-92, 10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing, Santorini Isl, 7/05/07. https://doi.org/10.1109/ISORC.2007.56

Time-predictable task preemption for real-time systems with direct-mapped instruction cache. / Kirner, Raimund; Puschner, Peter.
In: Procs of 10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing. ed. / M DeMiguel; V Kalogeraki; DH Kim. Institute of Electrical and Electronics Engineers (IEEE), 2007. p. 87-92.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Kirner, Raimund

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N1 - “This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”

PY - 2007

Y1 - 2007

N2 - Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded software is generally increasing, it becomes more and more complex to verify the correct temporal behavior of software, running on this high-end embedded computer systems. To achieve time-predictability the authors introduced a very rigid software execution model with distribution being realized based on the time-triggered communication model. In this paper we analyze the time-predictability of a preempting task-activation, running on a hardware with direct-mapped instruction caches. As one result we analyze why a task-preemption driven by a clock interrupt is not suitable to guarantee time-predictability. As a second result, we present a time-predictable task-preemption driven by an instruction counter.

AB - Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded software is generally increasing, it becomes more and more complex to verify the correct temporal behavior of software, running on this high-end embedded computer systems. To achieve time-predictability the authors introduced a very rigid software execution model with distribution being realized based on the time-triggered communication model. In this paper we analyze the time-predictability of a preempting task-activation, running on a hardware with direct-mapped instruction caches. As one result we analyze why a task-preemption driven by a clock interrupt is not suitable to guarantee time-predictability. As a second result, we present a time-predictable task-preemption driven by an instruction counter.

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BT - In: Procs of 10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing

A2 - DeMiguel, M

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PB - Institute of Electrical and Electronics Engineers (IEEE)

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ER -

Kirner R, Puschner P. Time-predictable task preemption for real-time systems with direct-mapped instruction cache. In DeMiguel M, Kalogeraki V, Kim DH, editors, In: Procs of 10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing. Institute of Electrical and Electronics Engineers (IEEE). 2007. p. 87-92 doi: 10.1109/ISORC.2007.56

Time-predictable task preemption for real-time systems with direct-mapped instruction cache

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