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A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

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A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS. / Zhang, Xinwang; Chen, Zipeng; Gao, Yanqiang; Xu, Yang; Liu, Bingqiao; Yu, Qian; Sun, Yichuang; Wang, Zhihua; Chi, Baoyong.

In: Microelectronics Journal, Vol. 72, 01.02.2018, p. 58-73.

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Zhang, Xinwang ; Chen, Zipeng ; Gao, Yanqiang ; Xu, Yang ; Liu, Bingqiao ; Yu, Qian ; Sun, Yichuang ; Wang, Zhihua ; Chi, Baoyong. / A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS. In: Microelectronics Journal. 2018 ; Vol. 72. pp. 58-73.

Bibtex

@article{d96a6c8d1e0246a9ae009deae245738f,
title = "A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS",
abstract = "A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.",
keywords = "CMOS, Digitally-assisted calibration, Low noise amplifier, RF, Soft-defined radio, Wireless receiver",
author = "Xinwang Zhang and Zipeng Chen and Yanqiang Gao and Yang Xu and Bingqiao Liu and Qian Yu and Yichuang Sun and Zhihua Wang and Baoyong Chi",
note = "{\textcopyright} 2017 Elsevier Ltd. All rights reserved. ",
year = "2018",
month = feb,
day = "1",
doi = "10.1016/j.mejo.2017.12.007",
language = "English",
volume = "72",
pages = "58--73",
journal = "Microelectronics Journal",
issn = "0026-2692",
publisher = "Elsevier Limited",

}

RIS

TY - JOUR

T1 - A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

AU - Zhang, Xinwang

AU - Chen, Zipeng

AU - Gao, Yanqiang

AU - Xu, Yang

AU - Liu, Bingqiao

AU - Yu, Qian

AU - Sun, Yichuang

AU - Wang, Zhihua

AU - Chi, Baoyong

N1 - © 2017 Elsevier Ltd. All rights reserved.

PY - 2018/2/1

Y1 - 2018/2/1

N2 - A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.

AB - A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.

KW - CMOS

KW - Digitally-assisted calibration

KW - Low noise amplifier

KW - RF

KW - Soft-defined radio

KW - Wireless receiver

UR - http://www.scopus.com/inward/record.url?scp=85038845659&partnerID=8YFLogxK

U2 - 10.1016/j.mejo.2017.12.007

DO - 10.1016/j.mejo.2017.12.007

M3 - Article

AN - SCOPUS:85038845659

VL - 72

SP - 58

EP - 73

JO - Microelectronics Journal

JF - Microelectronics Journal

SN - 0026-2692

ER -