University of Hertfordshire

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Original languageEnglish
JournalIET Circuits, Devices & Systems
Publication statusAccepted/In press - 21 Aug 2020

Abstract

A novel scheme for tunable CMOS transconductor robust against process and temperature variations is presented. The proposed configuration is a voltage controlled circuit based on a double NMOS transistor differential pairs connected in parallel, which has low power and high linearity. The process and temperature (PT) compensation is completed by two identical process and temperature compensation bias voltage generators (PTCBVG), which can guarantee the designed transconductor high tolerance for process and temperature variations. A complete CMOS transconductor with PTCBVG has been designed and simulated using 0.18μm technology. The effectiveness of PT compensation technique is proved. The simulation results of post‐layout are commensurate with pre‐layout. Post‐layout simulation results show that when temperature changes from −40‐85°C for different process corners (TT, SS, SF, FS, FF), the transconductance varies from 91.8‐123.6μS, temperature coefficient is below 1090ppm/°C, the total harmonic distortion is from −78‐−72dB@1MHz for 0.2VPPinput signal, ‐3dB bandwidth changes from 2.5‐5GHz, input referred noise varies from 78.1‐124.8nV/sqartHz@1MHz and DC power is from 1.5‐3.2mW.

Notes

© 2020 Institution of Engineering and Technology. This paper is a postprint of a paper submitted to and accepted for publication in IET Circuits, Devices & Systems and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at the IET Digital Library.

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