University of Hertfordshire

From the same journal

By the same authors

A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers

Research output: Contribution to journalArticlepeer-review

Standard

A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers. / Zhang, Xin; Wang, Chunhua; Sun, Yichuang; Peng, Haijun .

In: Journal of Circuits, Systems and Computers, Vol. 27, No. 3, 1850047 , 03.2018.

Research output: Contribution to journalArticlepeer-review

Harvard

APA

Vancouver

Author

Bibtex

@article{028f3bf2b8b04272b743e636be05464d,
title = "A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers",
abstract = "This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18μm CMOS technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8dB. The input and output reflection coefficients both are lower than -10.0dB over 2.5~11.5GHz. The input third-order intercept point (IIP3) is 5.6dBm at 8GHz and the noise figure (NF) is lower than 4.0dB. The LNA consumes 5.4mW power under a 1V supply voltage.",
author = "Xin Zhang and Chunhua Wang and Yichuang Sun and Haijun Peng",
note = "{\textcopyright} 2017 World Scientific Publishing Company. Electronic version of an article published as Journal of Circuits, Systems and Computers, Vol. 27, No. 03, 1850047, https://doi.org/10.1142/S0218126618500470.",
year = "2018",
month = mar,
doi = "10.1142/S0218126618500470",
language = "English",
volume = "27",
journal = "Journal of Circuits, Systems and Computers",
issn = "0218-1266",
publisher = "World Scientific Publishing Co. Pte Ltd",
number = "3",

}

RIS

TY - JOUR

T1 - A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers

AU - Zhang, Xin

AU - Wang, Chunhua

AU - Sun, Yichuang

AU - Peng, Haijun

N1 - © 2017 World Scientific Publishing Company. Electronic version of an article published as Journal of Circuits, Systems and Computers, Vol. 27, No. 03, 1850047, https://doi.org/10.1142/S0218126618500470.

PY - 2018/3

Y1 - 2018/3

N2 - This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18μm CMOS technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8dB. The input and output reflection coefficients both are lower than -10.0dB over 2.5~11.5GHz. The input third-order intercept point (IIP3) is 5.6dBm at 8GHz and the noise figure (NF) is lower than 4.0dB. The LNA consumes 5.4mW power under a 1V supply voltage.

AB - This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18μm CMOS technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8dB. The input and output reflection coefficients both are lower than -10.0dB over 2.5~11.5GHz. The input third-order intercept point (IIP3) is 5.6dBm at 8GHz and the noise figure (NF) is lower than 4.0dB. The LNA consumes 5.4mW power under a 1V supply voltage.

U2 - 10.1142/S0218126618500470

DO - 10.1142/S0218126618500470

M3 - Article

VL - 27

JO - Journal of Circuits, Systems and Computers

JF - Journal of Circuits, Systems and Computers

SN - 0218-1266

IS - 3

M1 - 1850047

ER -