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A Novel Multi-objective Optimisation Algorithm for Routability and Timing Driven Circuit Clustering on FPGAs. / Wang, Yuan; Albrecht Trefzer, Martin; Jonathan Bale, Simon; Alfred Walker, James; Martin Tyrrell, Andrew.

In: IET Computers and Digital Techniques, 28.10.2018.

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Wang Y, Albrecht Trefzer M, Jonathan Bale S, Alfred Walker J, Martin Tyrrell A. A Novel Multi-objective Optimisation Algorithm for Routability and Timing Driven Circuit Clustering on FPGAs. IET Computers and Digital Techniques. 2018 Oct 28.

Author

Wang, Yuan ; Albrecht Trefzer, Martin ; Jonathan Bale, Simon ; Alfred Walker, James ; Martin Tyrrell, Andrew. / A Novel Multi-objective Optimisation Algorithm for Routability and Timing Driven Circuit Clustering on FPGAs. In: IET Computers and Digital Techniques. 2018.

Bibtex

@article{522644499b1f4fcdaa125375c879ed04,
title = "A Novel Multi-objective Optimisation Algorithm for Routability and Timing Driven Circuit Clustering on FPGAs",
abstract = "Circuit clustering algorithms fit synthesised circuits into FPGA configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g., power and delay. In this paper, we present a method based on multi-objective genetic algorithm (MOGA) to facilitate circuit clustering. We address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. Our new approach has been validated using the {"}Golden 20{"} MCNC benchmark circuits that are regularly used in FPGA-related literature. The results show that the method proposed in this paper achieves improvements of up to 50% in clustering, routability and timing when compared to state-of-the-art approaches including VPack, T-VPack, RPack, DPack, HDPack, MOPack and iRAC. Key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real-world circuit design on FPGA, providing device utilisation at increased design performance.",
author = "Yuan Wang and {Albrecht Trefzer}, Martin and {Jonathan Bale}, Simon and {Alfred Walker}, James and {Martin Tyrrell}, Andrew",
note = "This paper is a postprint of a paper submitted to and accepted for publication in IET Computers and Digital Techniques and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at the IET Digital Library",
year = "2018",
month = oct,
day = "28",
language = "English",
journal = "IET Computers and Digital Techniques",
issn = "1751-8601",
publisher = "Institution of Engineering and Technology",

}

RIS

TY - JOUR

T1 - A Novel Multi-objective Optimisation Algorithm for Routability and Timing Driven Circuit Clustering on FPGAs

AU - Wang, Yuan

AU - Albrecht Trefzer, Martin

AU - Jonathan Bale, Simon

AU - Alfred Walker, James

AU - Martin Tyrrell, Andrew

N1 - This paper is a postprint of a paper submitted to and accepted for publication in IET Computers and Digital Techniques and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at the IET Digital Library

PY - 2018/10/28

Y1 - 2018/10/28

N2 - Circuit clustering algorithms fit synthesised circuits into FPGA configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g., power and delay. In this paper, we present a method based on multi-objective genetic algorithm (MOGA) to facilitate circuit clustering. We address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. Our new approach has been validated using the "Golden 20" MCNC benchmark circuits that are regularly used in FPGA-related literature. The results show that the method proposed in this paper achieves improvements of up to 50% in clustering, routability and timing when compared to state-of-the-art approaches including VPack, T-VPack, RPack, DPack, HDPack, MOPack and iRAC. Key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real-world circuit design on FPGA, providing device utilisation at increased design performance.

AB - Circuit clustering algorithms fit synthesised circuits into FPGA configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g., power and delay. In this paper, we present a method based on multi-objective genetic algorithm (MOGA) to facilitate circuit clustering. We address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. Our new approach has been validated using the "Golden 20" MCNC benchmark circuits that are regularly used in FPGA-related literature. The results show that the method proposed in this paper achieves improvements of up to 50% in clustering, routability and timing when compared to state-of-the-art approaches including VPack, T-VPack, RPack, DPack, HDPack, MOPack and iRAC. Key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real-world circuit design on FPGA, providing device utilisation at increased design performance.

M3 - Article

JO - IET Computers and Digital Techniques

JF - IET Computers and Digital Techniques

SN - 1751-8601

ER -