University of Hertfordshire

By the same authors

A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS

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Original languageEnglish
Number of pages4
JournalIEEE Microwave and Wireless Components Letters
Early online date25 Mar 2022
DOIs
Publication statusE-pub ahead of print - 25 Mar 2022

Abstract

Power-handling capability of bulk CMOS-based single-pole double-throw switch operating in millimetre-wave and sub-THz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100 GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss of 3.5 dB and an isolation of 18 dB. The total area of the chip is only 0.14 mm2.

Notes

© 2022 IEEE -This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/LMWC.2022.3159529

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