University of Hertfordshire

By the same authors

A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS

Research output: Contribution to journal › Article › peer-review

Standard

A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS. / Chen, Lisheng; Chen, Lang; Ge, Zeyu; Sun, Yichuang; Hamilton, Tara; Zhu, Xi.

In: IEEE Microwave and Wireless Components Letters, 25.03.2022.

Research output: Contribution to journal › Article › peer-review

Harvard

Chen, L, Chen, L, Ge, Z, Sun, Y, Hamilton, T & Zhu, X 2022, 'A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS', IEEE Microwave and Wireless Components Letters. https://doi.org/10.1109/LMWC.2022.3159529

APA

Chen, L., Chen, L., Ge, Z., Sun, Y., Hamilton, T., & Zhu, X. (2022). A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS. IEEE Microwave and Wireless Components Letters. https://doi.org/10.1109/LMWC.2022.3159529

Vancouver

Chen L, Chen L, Ge Z, Sun Y, Hamilton T, Zhu X. A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS. IEEE Microwave and Wireless Components Letters. 2022 Mar 25. https://doi.org/10.1109/LMWC.2022.3159529

Author

Chen, Lisheng ; Chen, Lang ; Ge, Zeyu ; Sun, Yichuang ; Hamilton, Tara ; Zhu, Xi. / A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS. In: IEEE Microwave and Wireless Components Letters. 2022.

Bibtex

@article{efd0cf99a9c7464da3bf4c035d75579d,
title = "A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS",
abstract = "Power-handling capability of bulk CMOS-based single-pole double-throw switch operating in millimetre-wave and sub-THz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100 GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss of 3.5 dB and an isolation of 18 dB. The total area of the chip is only 0.14 mm2.",
author = "Lisheng Chen and Lang Chen and Zeyu Ge and Yichuang Sun and Tara Hamilton and Xi Zhu",
note = "{\textcopyright} 2022 IEEE -This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/LMWC.2022.3159529",
year = "2022",
month = mar,
day = "25",
doi = "10.1109/LMWC.2022.3159529",
language = "English",
journal = "IEEE Microwave and Wireless Components Letters",
issn = "1531-1309",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

RIS

TY - JOUR

T1 - A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS

AU - Chen, Lisheng

AU - Chen, Lang

AU - Ge, Zeyu

AU - Sun, Yichuang

AU - Hamilton, Tara

AU - Zhu, Xi

N1 - © 2022 IEEE -This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/LMWC.2022.3159529

PY - 2022/3/25

Y1 - 2022/3/25

N2 - Power-handling capability of bulk CMOS-based single-pole double-throw switch operating in millimetre-wave and sub-THz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100 GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss of 3.5 dB and an isolation of 18 dB. The total area of the chip is only 0.14 mm2.

AB - Power-handling capability of bulk CMOS-based single-pole double-throw switch operating in millimetre-wave and sub-THz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100 GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss of 3.5 dB and an isolation of 18 dB. The total area of the chip is only 0.14 mm2.

U2 - 10.1109/LMWC.2022.3159529

DO - 10.1109/LMWC.2022.3159529

M3 - Article

JO - IEEE Microwave and Wireless Components Letters

JF - IEEE Microwave and Wireless Components Letters

SN - 1531-1309

ER -