University of Hertfordshire

By the same authors

Avoiding timing anomalies using code transformations

Research output: Chapter in Book/Report/Conference proceedingConference contribution


  • 905602

    Accepted author manuscript, 308 KB, PDF document

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Original languageEnglish
Title of host publicationIn : Proceedings of the 13th IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC'10)
Number of pages10
ISBN (Print)978-1-4244-7083-9
Publication statusPublished - 2010


Divide-and-conquer approaches to worst-case execution-time analysis (WCET analysis) pose a safety risk when applied to code for complex modern processors: Interferences between the hardware acceleration mechanisms of these processors lead to timing anomalies, i.e., a local timing change causes an either larger or inverse change of the global timing. This phenomenon may result in dangerous WCET underestimation. This paper presents intermediate results of our work on strategies for eliminating timing anomalies. These strategies are purely based on the modification of software, i.e., they do not require any changes to hardware. In an effort to eliminate the timing anomalies originating from the processor's out-of-order instruction pipeline, we explored different methods of inserting instructions in the program code that render the dynamic instruction scheduler inoperative. We explain how the proposed strategies remove the timing anomalies caused by the pipeline. In the absence of working solutions for timing analysis for these complex processors, we chose portable metrics from compiler construction to assess the properties of our algorithms.


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