University of Hertfordshire

From the same journal

Clock faults induced min and max delay violations

Research output: Contribution to journalArticlepeer-review

  • D. Rossi
  • M. Omaña
  • J. M. Cazeaux
  • C. Metra
  • T. M. Mak
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Original languageEnglish
Pages (from-to)111-123
Number of pages13
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Publication statusPublished - 2014


In this paper, we show that clock faults producing duty-cycle variations, which have been proven very likely, can give rise to min or max delay violations. This mandates new, specific testing approaches for clock faults, to avoid them to compromise the system correct operation in the field, with dramatic effects on product quality and defect level. We then introduce a new scheme that can be employed to detect the clock faults causing duty-cycle variations.

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