University of Hertfordshire

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Coarse-grained Online Monitoring of BTI Aging by Reusing Power Gating Infrastructure

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  • Vasileios Tenentes
  • Daniele Rossi
  • Sheng Yang
  • Saqib Khursheed
  • Bashir M. Al-Hashimi
  • Steve R. Gunn
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Original languageEnglish
Pages (from-to)1397 - 1407
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Early online date2 Dec 2016
Publication statusPublished - 1 Apr 2017


In this paper, we present a novel coarse-grained technique for monitoring online the bias temperature instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during standby operations, the value of which depends on the threshold voltage of the CMOS devices in a power-gated design (PGD). It does not require any distributed sensors, because the virtual-power-network is already distributed in a PGD. It consists of a hardware block for measuring the discharge time concurrently with normal standby operations and a processing block for estimating the BTI aging status of the PGD according to collected measurements. Through SPICE simulation, we demonstrate that the BTI aging estimation error of the proposed technique is less than 1% and 6.2% for PGDs with static operating frequency and dynamic voltage and frequency scaling, respectively. Its area cost is also found negligible. The power gating minimum idle time (MIT) cost induced by the energy consumed for monitoring the discharge time is evaluated on two scalar machine models using either x86 or ARM instruction sets. It is found less than 1.3× and 1.45× the original power gating MIT, respectively. We validate the proposed technique through accelerated aging experiments conducted with five actual chips that contain an ARM cortex M0 processor, manufactured with a 65 nm CMOS technology.


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