University of Hertfordshire

Developing the Hatfield Superscalar architecture cache simulator

Research output: Book/ReportOther report

Standard

Developing the Hatfield Superscalar architecture cache simulator. / Tate, D.

University of Hertfordshire, 1998. (UH Computer Science Technical Report; Vol. 318).

Research output: Book/ReportOther report

Harvard

Tate, D 1998, Developing the Hatfield Superscalar architecture cache simulator. UH Computer Science Technical Report, vol. 318, University of Hertfordshire.

APA

Tate, D. (1998). Developing the Hatfield Superscalar architecture cache simulator. (UH Computer Science Technical Report; Vol. 318). University of Hertfordshire.

Vancouver

Tate D. Developing the Hatfield Superscalar architecture cache simulator. University of Hertfordshire, 1998. (UH Computer Science Technical Report).

Author

Tate, D. / Developing the Hatfield Superscalar architecture cache simulator. University of Hertfordshire, 1998. (UH Computer Science Technical Report).

Bibtex

@book{050be24364dc464a9790fb60d71d52de,
title = "Developing the Hatfield Superscalar architecture cache simulator",
abstract = "A great deal of the current research into computer architecture is directed at Multiple Instruction Issue (MII) processors. These processors have the ability to issue, process and retire more than one instruction per cycle. Multiple instructions can be simultaneously issued when there are no dependencies between them. MII architectures can be split into two diverse types: VLIW and superscalar. These types are differentiated by the time at which the instructions are scheduled into groups that could be issued in parallel. A VLIW processor relies on the complier to generate fixed sized groups of instructions, while a superscalar processor relies on the processor to dynamically generate groups of independent instructions. Current work at the University of Hertfordshire is focused on developing a processor that combines the best features of both VLIW and superscalar processors.",
author = "D. Tate",
year = "1998",
language = "English",
series = "UH Computer Science Technical Report",
publisher = "University of Hertfordshire",

}

RIS

TY - BOOK

T1 - Developing the Hatfield Superscalar architecture cache simulator

AU - Tate, D.

PY - 1998

Y1 - 1998

N2 - A great deal of the current research into computer architecture is directed at Multiple Instruction Issue (MII) processors. These processors have the ability to issue, process and retire more than one instruction per cycle. Multiple instructions can be simultaneously issued when there are no dependencies between them. MII architectures can be split into two diverse types: VLIW and superscalar. These types are differentiated by the time at which the instructions are scheduled into groups that could be issued in parallel. A VLIW processor relies on the complier to generate fixed sized groups of instructions, while a superscalar processor relies on the processor to dynamically generate groups of independent instructions. Current work at the University of Hertfordshire is focused on developing a processor that combines the best features of both VLIW and superscalar processors.

AB - A great deal of the current research into computer architecture is directed at Multiple Instruction Issue (MII) processors. These processors have the ability to issue, process and retire more than one instruction per cycle. Multiple instructions can be simultaneously issued when there are no dependencies between them. MII architectures can be split into two diverse types: VLIW and superscalar. These types are differentiated by the time at which the instructions are scheduled into groups that could be issued in parallel. A VLIW processor relies on the complier to generate fixed sized groups of instructions, while a superscalar processor relies on the processor to dynamically generate groups of independent instructions. Current work at the University of Hertfordshire is focused on developing a processor that combines the best features of both VLIW and superscalar processors.

M3 - Other report

T3 - UH Computer Science Technical Report

BT - Developing the Hatfield Superscalar architecture cache simulator

PB - University of Hertfordshire

ER -