University of Hertfordshire

By the same authors

Dynamic Row Activation Mechanism for Multi-Core Systems

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Original languageEnglish
Title of host publicationCF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers
PublisherThe Association for Computing Machinery
Number of pages9
Publication statusPublished - 13 May 2021
Event18th ACM International Conference on Computing Frontiers 2021
(CF 2021)
- , Italy
Duration: 11 May 202113 May 2021


Conference18th ACM International Conference on Computing Frontiers 2021
(CF 2021)
Internet address


The power that stems from modern DRAM devices represents a sig- nificant portion of the overall system power in modern computing systems. In multi-core systems, the competing cores share the same memory banks. The memory contention between these cores may lead to activate a large DRAM row only to access a small portion of data. This row over-fetching problem wastes a significant DRAM activation power with a slight performance gain.
In this paper, we propose a dynamic row activation mechanism, in which the optimal size of DRAM rows is detected at run-time based on monitoring the behavioural changes of the memory re- quests in accessing sub-rows. The proposed mechanism aims at providing significant memory power savings, reducing the average memory access latency, and maintaining the full DRAM bandwidth. Our experimental results using four-core multi-programming work- loads revealed that the proposed mechanism in this study can achieve both significant memory power reduction and average DRAM memory access latency improvement with negligible area overhead.


© 2021 by the Association for Computing Machinery, Inc. This is the accepted manuscript version of an article which has been published in final form at

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