University of Hertfordshire

By the same authors

Dynamic Row Activation Mechanism for Multi-Core Systems

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Original languageEnglish
Title of host publicationDynamic Row Activation Mechanism for Multi-Core Systems
PublisherAssociation for Computing Machinery (ACM)
Number of pages9
Publication statusAccepted/In press - 25 Mar 2021


The power that stems from modern DRAM devices represents a sig- nificant portion of the overall system power in modern computing systems. In multi-core systems, the competing cores share the same memory banks. The memory contention between these cores may lead to activate a large DRAM row only to access a small portion of data. This row over-fetching problem wastes a significant DRAM activation power with a slight performance gain.
In this paper, we propose a dynamic row activation mechanism, in which the optimal size of DRAM rows is detected at run-time based on monitoring the behavioural changes of the memory re- quests in accessing sub-rows. The proposed mechanism aims at providing significant memory power savings, reducing the average memory access latency, and maintaining the full DRAM bandwidth. Our experimental results using four-core multi-programming work- loads revealed that the proposed mechanism in this study can achieve both significant memory power reduction and average DRAM memory access latency improvement with negligible area overhead.

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