University of Hertfordshire

By the same authors

Dynamic Row Activation Mechanism for Multi-Core Systems

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Standard

Dynamic Row Activation Mechanism for Multi-Core Systems. / Alawneh, Tareq A.; Kirner, Raimund; Menon, Catherine.

CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers. The Association for Computing Machinery, 2021. p. 21-29.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Harvard

Alawneh, TA, Kirner, R & Menon, C 2021, Dynamic Row Activation Mechanism for Multi-Core Systems. in CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers. The Association for Computing Machinery, pp. 21-29, 18th ACM International Conference on Computing Frontiers 2021
(CF 2021), Italy, 11/05/21. https://doi.org/10.1145/3457388.3458660

APA

Alawneh, T. A., Kirner, R., & Menon, C. (2021). Dynamic Row Activation Mechanism for Multi-Core Systems. In CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers (pp. 21-29). The Association for Computing Machinery. https://doi.org/10.1145/3457388.3458660

Vancouver

Alawneh TA, Kirner R, Menon C. Dynamic Row Activation Mechanism for Multi-Core Systems. In CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers. The Association for Computing Machinery. 2021. p. 21-29 https://doi.org/10.1145/3457388.3458660

Author

Alawneh, Tareq A. ; Kirner, Raimund ; Menon, Catherine. / Dynamic Row Activation Mechanism for Multi-Core Systems. CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers. The Association for Computing Machinery, 2021. pp. 21-29

Bibtex

@inproceedings{7f47106df8eb47258840550c7a8fed67,
title = "Dynamic Row Activation Mechanism for Multi-Core Systems",
abstract = "The power that stems from modern DRAM devices represents a sig- nificant portion of the overall system power in modern computing systems. In multi-core systems, the competing cores share the same memory banks. The memory contention between these cores may lead to activate a large DRAM row only to access a small portion of data. This row over-fetching problem wastes a significant DRAM activation power with a slight performance gain.In this paper, we propose a dynamic row activation mechanism, in which the optimal size of DRAM rows is detected at run-time based on monitoring the behavioural changes of the memory re- quests in accessing sub-rows. The proposed mechanism aims at providing significant memory power savings, reducing the average memory access latency, and maintaining the full DRAM bandwidth. Our experimental results using four-core multi-programming work- loads revealed that the proposed mechanism in this study can achieve both significant memory power reduction and average DRAM memory access latency improvement with negligible area overhead.",
author = "Alawneh, {Tareq A.} and Raimund Kirner and Catherine Menon",
note = "{\textcopyright} 2021 by the Association for Computing Machinery, Inc. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1145/3457388.3458660; 18th ACM International Conference on Computing Frontiers 2021<br/>(CF 2021) ; Conference date: 11-05-2021 Through 13-05-2021",
year = "2021",
month = may,
day = "13",
doi = "10.1145/3457388.3458660",
language = "English",
pages = "21--29",
booktitle = "CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers",
publisher = "The Association for Computing Machinery",
url = "https://www.computingfrontiers.org/2021/",

}

RIS

TY - GEN

T1 - Dynamic Row Activation Mechanism for Multi-Core Systems

AU - Alawneh, Tareq A.

AU - Kirner, Raimund

AU - Menon, Catherine

N1 - © 2021 by the Association for Computing Machinery, Inc. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1145/3457388.3458660

PY - 2021/5/13

Y1 - 2021/5/13

N2 - The power that stems from modern DRAM devices represents a sig- nificant portion of the overall system power in modern computing systems. In multi-core systems, the competing cores share the same memory banks. The memory contention between these cores may lead to activate a large DRAM row only to access a small portion of data. This row over-fetching problem wastes a significant DRAM activation power with a slight performance gain.In this paper, we propose a dynamic row activation mechanism, in which the optimal size of DRAM rows is detected at run-time based on monitoring the behavioural changes of the memory re- quests in accessing sub-rows. The proposed mechanism aims at providing significant memory power savings, reducing the average memory access latency, and maintaining the full DRAM bandwidth. Our experimental results using four-core multi-programming work- loads revealed that the proposed mechanism in this study can achieve both significant memory power reduction and average DRAM memory access latency improvement with negligible area overhead.

AB - The power that stems from modern DRAM devices represents a sig- nificant portion of the overall system power in modern computing systems. In multi-core systems, the competing cores share the same memory banks. The memory contention between these cores may lead to activate a large DRAM row only to access a small portion of data. This row over-fetching problem wastes a significant DRAM activation power with a slight performance gain.In this paper, we propose a dynamic row activation mechanism, in which the optimal size of DRAM rows is detected at run-time based on monitoring the behavioural changes of the memory re- quests in accessing sub-rows. The proposed mechanism aims at providing significant memory power savings, reducing the average memory access latency, and maintaining the full DRAM bandwidth. Our experimental results using four-core multi-programming work- loads revealed that the proposed mechanism in this study can achieve both significant memory power reduction and average DRAM memory access latency improvement with negligible area overhead.

U2 - 10.1145/3457388.3458660

DO - 10.1145/3457388.3458660

M3 - Conference contribution

SP - 21

EP - 29

BT - CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers

PB - The Association for Computing Machinery

T2 - 18th ACM International Conference on Computing Frontiers 2021<br/>(CF 2021)

Y2 - 11 May 2021 through 13 May 2021

ER -