University of Hertfordshire

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Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

Research output: Contribution to journalArticlepeer-review


  • Daniele Rossi
  • Vasileios Tenentes
  • Sudhakar M. Reddy
  • Bashir M. Al-Hashimi
  • Andrew Brown
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Original languageEnglish
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early online date19 Jul 2017
Publication statusE-pub ahead of print - 19 Jul 2017


In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling (DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI) in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in sub-threshold current due to BTI aging. We develop a simulation framework to evaluate trade-offs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead.


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