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Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

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Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories. / Rossi, Daniele; Tenentes, Vasileios; Reddy, Sudhakar M. ; Al-Hashimi, Bashir M.; Brown, Andrew.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19.07.2017.

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Rossi, Daniele ; Tenentes, Vasileios ; Reddy, Sudhakar M. ; Al-Hashimi, Bashir M. ; Brown, Andrew. / Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2017.

Bibtex

@article{d58eab7242d442e58abc85597320f6f6,
title = "Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories",
abstract = "In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling (DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI) in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in sub-threshold current due to BTI aging. We develop a simulation framework to evaluate trade-offs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead.",
keywords = "Drowsy memory, Dynamic Voltage Scaling, Bias Temperature Instability, Static power, Soft Error Rate, Noise margin",
author = "Daniele Rossi and Vasileios Tenentes and Reddy, {Sudhakar M.} and Al-Hashimi, {Bashir M.} and Andrew Brown",
note = "Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.",
year = "2017",
month = jul,
day = "19",
doi = "10.1109/TCAD.2017.2729399",
language = "English",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
issn = "0278-0070",
publisher = "IEEE",

}

RIS

TY - JOUR

T1 - Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

AU - Rossi, Daniele

AU - Tenentes, Vasileios

AU - Reddy, Sudhakar M.

AU - Al-Hashimi, Bashir M.

AU - Brown, Andrew

N1 - Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.

PY - 2017/7/19

Y1 - 2017/7/19

N2 - In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling (DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI) in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in sub-threshold current due to BTI aging. We develop a simulation framework to evaluate trade-offs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead.

AB - In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling (DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI) in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in sub-threshold current due to BTI aging. We develop a simulation framework to evaluate trade-offs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead.

KW - Drowsy memory

KW - Dynamic Voltage Scaling

KW - Bias Temperature Instability

KW - Static power

KW - Soft Error Rate

KW - Noise margin

U2 - 10.1109/TCAD.2017.2729399

DO - 10.1109/TCAD.2017.2729399

M3 - Article

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

ER -