University of Hertfordshire

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Original languageEnglish
Article number5921
Number of pages16
JournalSensors
Volume20
Issue20
DOIs
Publication statusPublished - 20 Oct 2020

Abstract

In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128 pixel CMOS imager. Reduction of the PRNU to ∼0.5 LSB has been achieved. Linearity improvement technique has also been proposed which allows for integral non-linearity (INL) reduction to ∼0.5 LSB. Measurements confirm the proposed approach.

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© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

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