University of Hertfordshire

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iHARP a Multiple Instruction Issue Processor Chip Incorporating RISC and VLIW Design Features

Research output: Contribution to journalArticlepeer-review

  • S.A. Trainis
  • P. Findlay
  • G.B. Steven
  • R.G. Adams
  • D. McHale
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Original languageEnglish
Pages (from-to)115-119
JournalMicroelectronics Journal
Publication statusPublished - 1992


RISC (Reduced Instruction Set Computers) processors have established an impressive performance standard by executing one instruction in each processor cycle. More recently, VLIW (Very Long Instruction Word) and superscalar architectures have attempted to improve processor performance by fetching and dispatching multiple instructions in each cycle. This paper presents the Hatfield Advanced RISC Processor (iHARP). iHARP is a parallel pipelined reduced instructions set processor that is currently under development at Hatfield Polytechnic. Earlier work at Hatfield centred around the design of an abstract HARP architectural model [1]. iHARP is a physical realisation of the HARP architectural model within the constraints of a single VLSI chip. The major aim of the HARP project is to develop a VLIW RISC processor capable of executing more than one instruction per clock cycle.


Original article can be found at : Copyright Elsevier Ltd. DOI: 10.1016/0026-2692(92)90043-Z [Full text of this article is not available in the UHRA]

ID: 89576