University of Hertfordshire

From the same journal

By the same authors

Documents

  • 904848

    Accepted author manuscript, 1.03 MB, PDF document

View graph of relations
Original languageEnglish
Pages (from-to)93-103
JournalIET Circuits, Devices & Systems
Volume7
Issue2
DOIs
Publication statusPublished - Mar 2013

Abstract

Number plate localisation is a very important stage in an Automatic Number Plate Recognition (ANPR) system and is computationally intensive. This paper presents a low complexity with high detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplierless architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images respectively, both with a resolution of "640×480" , have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms whilst achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.

ID: 1047057