University of Hertfordshire

From the same journal

By the same authors

Standard

Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation. / Zhai, Xiaojun; Bensaali, Faycal; Ramalingam, Soodamani.

In: IET Circuits, Devices & Systems, Vol. 7, No. 2, 03.2013, p. 93-103.

Research output: Contribution to journalArticlepeer-review

Harvard

APA

Vancouver

Author

Bibtex

@article{d6d4804e6a8e453984b5b1d38a437109,
title = "Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation",
abstract = "Number plate localisation is a very important stage in an Automatic Number Plate Recognition (ANPR) system and is computationally intensive. This paper presents a low complexity with high detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplierless architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images respectively, both with a resolution of {"}640×480{"} , have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms whilst achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.",
author = "Xiaojun Zhai and Faycal Bensaali and Soodamani Ramalingam",
year = "2013",
month = mar,
doi = "10.1049/iet-cds.2012.0064",
language = "English",
volume = "7",
pages = "93--103",
journal = "IET Circuits, Devices & Systems",
issn = "1751-858X",
publisher = "Institution of Engineering and Technology",
number = "2",

}

RIS

TY - JOUR

T1 - Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation

AU - Zhai, Xiaojun

AU - Bensaali, Faycal

AU - Ramalingam, Soodamani

PY - 2013/3

Y1 - 2013/3

N2 - Number plate localisation is a very important stage in an Automatic Number Plate Recognition (ANPR) system and is computationally intensive. This paper presents a low complexity with high detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplierless architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images respectively, both with a resolution of "640×480" , have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms whilst achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.

AB - Number plate localisation is a very important stage in an Automatic Number Plate Recognition (ANPR) system and is computationally intensive. This paper presents a low complexity with high detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplierless architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images respectively, both with a resolution of "640×480" , have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms whilst achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.

U2 - 10.1049/iet-cds.2012.0064

DO - 10.1049/iet-cds.2012.0064

M3 - Article

VL - 7

SP - 93

EP - 103

JO - IET Circuits, Devices & Systems

JF - IET Circuits, Devices & Systems

SN - 1751-858X

IS - 2

ER -