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Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

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Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. / Omana, Martin; Rossi, Daniele; Fuzzi, Filippo; Metra, Cecilia; Tirumurti, Chandra; Galivanche, Rajesh.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 1, 31.01.2017, p. 238 - 246.

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Omana, Martin ; Rossi, Daniele ; Fuzzi, Filippo ; Metra, Cecilia ; Tirumurti, Chandra ; Galivanche, Rajesh. / Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017 ; Vol. 25, No. 1. pp. 238 - 246.

Bibtex

@article{285492533b7b4316bc66bdc433f520f4,
title = "Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST",
abstract = "The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC.",
keywords = "Logic BIST (LBIST), microprocessors,, power droop (PD), test quality",
author = "Martin Omana and Daniele Rossi and Filippo Fuzzi and Cecilia Metra and Chandra Tirumurti and Rajesh Galivanche",
note = "This document is the Accepted Manuscript version of the following article: Martin Omana, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandrasekharan Chandra Tirumurti, and Rajesh Galivanche, {\textquoteleft}Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST{\textquoteright}, IEEE Transactions on Very Large Scale Integration (VLSI) System, Vol 25 (1): 238-246, January 2017, DOI: https://doi.org/10.1109/TVLSI.2016.2572606. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. ",
year = "2017",
month = jan,
day = "31",
doi = "10.1109/TVLSI.2016.2572606",
language = "English",
volume = "25",
pages = "238 -- 246",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "IEEE",
number = "1",

}

RIS

TY - JOUR

T1 - Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

AU - Omana, Martin

AU - Rossi, Daniele

AU - Fuzzi, Filippo

AU - Metra, Cecilia

AU - Tirumurti, Chandra

AU - Galivanche, Rajesh

N1 - This document is the Accepted Manuscript version of the following article: Martin Omana, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandrasekharan Chandra Tirumurti, and Rajesh Galivanche, ‘Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST’, IEEE Transactions on Very Large Scale Integration (VLSI) System, Vol 25 (1): 238-246, January 2017, DOI: https://doi.org/10.1109/TVLSI.2016.2572606. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.

PY - 2017/1/31

Y1 - 2017/1/31

N2 - The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC.

AB - The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC.

KW - Logic BIST (LBIST)

KW - microprocessors,

KW - power droop (PD)

KW - test quality

U2 - 10.1109/TVLSI.2016.2572606

DO - 10.1109/TVLSI.2016.2572606

M3 - Article

VL - 25

SP - 238

EP - 246

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 1

ER -